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EISA System Architecture, Tom Shanley, Don Anderson, 1995

EISA System Architecture, Tom Shanley, Don Anderson, 1995

EISA System Architecture, Tom Shanley, Don Anderson, 1995.
  EISA System Architecture is divided into two major parts:
• Part One — The EISA Specification
• Part Two — The Intel 82350DT EISA Chip Set
Part One provides a detailed explanation of the ISA enhancements as set forth in the EISA specification, while Part Two provides a detailed description of the features implemented by the Intel 82350DT chip set. The following paragraphs provide a summary of each section.

Bus Arbitration.
The EISA system board logic also provides a centralized arbitration scheme, allowing efficient bus sharing among the main CPU, multiple EISA bus master cards and DMA channels. The centralized arbitration supports preemption of an active bus master or DMA device and can reset a device that does not release the bus after preemption.

The EISA arbitration method grants the bus to DMA devices, DRAM refresh, bus masters and the main CPU on a fair, rotational basis. The rotational scheme provides a short latency for DMA devices to assure compatibility with ISA DMA devices. Bus masters and the CPU, which typically have buffering available, have longer, but predictable latencies.

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